There are a number of challenges that scaling of conventional planar metal-oxide-semiconductor field-effect transistors (MOSFETs) are faced with. For example, threshold swing degradation, large drain-induced barrier lowering (DIBL), device characteristics fluctuations, and leakage are among the most common problems that may be addressed by 3-D device structures. FinFETs are 3-D device structures that can be used in nano-scale complementary metal-oxide-semiconductor (CMOS) and high-density memory applications.
FinFET devices are divided into two categories, bulk finFETs and silicon-on-insulator (SOI) finFETs. In bulk finFET devices, which are more common in 14 nm and/or 16 nm technology, the fin can be formed on the bulk silicon (e.g., silicon substrate). In SOI finFET the fin is isolated from the bulk silicon by a silicon oxide (e.g., SiO2) layer. The bulk finFET can be produced at low cost, low defect density, high heat transfer to substrate, and good process control. In some bulk finFETs, in order to prevent punch-through leakage from fin to the substrate, punch-through stop implants (e.g., n-type or p-type) can be used for junction isolation. However, punch-through stop implants may not be able to solve the leakage issue completely. Therefore, in future bulk finFET devices, dielectric isolation may be the preferred choice to address the leakage problem.